Dfsdm Interrupt And Status Register (Dfsdm_Fltxisr) - ST STM32F413 Reference Manual

RM0430
Bit 2 JOVRIE: Injected data overrun interrupt enable
0: Injected data overrun interrupt is disabled
1: Injected data overrun interrupt is enabled
Please see the explanation of JOVRF in DFSDM_FLTxISR.
Bit 1 REOCIE: Regular end of conversion interrupt enable
0: Regular end of conversion interrupt is disabled
1: Regular end of conversion interrupt is enabled
Please see the explanation of REOCF in DFSDM_FLTxISR.
Bit 0 JEOCIE: Injected end of conversion interrupt enable
0: Injected end of conversion interrupt is disabled
1: Injected end of conversion interrupt is enabled
Please see the explanation of JEOCF in DFSDM_FLTxISR.
15.8.3

DFSDM interrupt and status register (DFSDM_FLTxISR)

Address offset: 0x108 + 0x80 * x, x = 0...3
Reset value: 0x00FF 0000
31 30 29
r r r
15 14 13
Res. RCIP JCIP Res.
r r
Bits 31:24 SCDF[7:0]: short-circuit detector flag
SDCF[y]=0: No short-circuit detector event occurred on channel y
SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the
DFSDM_CHyAWSCDR registers
This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in
the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given
channel
is disabled).
Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
Bits 23:16 CKABF[7:0]: Clock absence flag
CKABF[y]=0: Clock signal on channel y is present.
CKABF[y]=1: Clock signal on channel y is not present.
Given y bit is set by hardware when clock absence is detected on channel y. It is held at
CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at
CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by
software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register.
Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
Bit 15 Reserved, must be kept at reset value.
28 27 26 25
SCDF[7:0]
r r r r
12 11 10 9
Res. Res. Res.
DocID029473 Rev 3
Digital filter for sigma delta modulators (DFSDM)
24 23 22 21
r r r r
8 7 6 5
Res. Res. Res. Res.
20 19 18 17
CKABF[7:0]
r r r
4 3 2
AWDF ROVRF JOVRF REOCF JEOCF
r r r
16
r r
1 0
r r
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