Supported Audio Protocols - ST STM32F413 Reference Manual

Serial peripheral interface/ inter-IC sound (SPI/I2S)
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29.6 I S functional description
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29.6.1 I S general description
The block diagram of the I
The SPI can function as an audio I
the I2SMOD bit in the SPIx_I2SCFGR register). This interface mainly uses the same pins,
flags and interrupts as the SPI.
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The I S shares three common pins with the SPI:
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SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time-
multiplexed data channels (in half-duplex mode only).
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WS: Word Select (mapped on the NSS pin) is the data control signal output in master
mode and input in slave mode.
•
CK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode
and serial clock input in slave mode.
An additional pin can be used when a master clock output is needed for some external
audio devices:
•
MCK: Master Clock (mapped separately) is used, when the I
mode (and when the MCKOE bit in the SPIx_I2SPR register is set), to output this
additional clock generated at a preconfigured frequency rate equal to 256 × f
f is the audio sampling frequency.
S
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The I S uses its own clock generator to produce the communication clock when it is set in
master mode. This clock generator is also the source of the master clock output. Two
additional registers are available in I
configuration SPIx_I2SPR and the other one is a generic I
SPIx_I2SCFGR (audio standard, slave/master mode, data format, packet frame, clock
polarity, etc.).
The SPIx_CR1 register and all CRC registers are not used in the I
SSOE bit in the SPIx_CR2 register and the MODF and CRCERR bits in the SPIx_SR are
not used.
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The I S uses the same SPI register for data transfer (SPIx_DR) in 16-bit wide mode.
29.6.2

Supported audio protocols

The three-line bus has to handle only audio data generally time-multiplexed on two
channels: the right channel and the left channel. However there is only one 16-bit register
for transmission or reception. So, it is up to the software to write into the data register the
appropriate value corresponding to each channel side, or to read the data from the data
register and to identify the corresponding channel by checking the CHSIDE bit in the
SPIx_SR register. Channel left is always sent first followed by the channel right (CHSIDE
has no meaning for the PCM protocol).
Four data and packet frames are available. Data may be sent with a format of:
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16-bit data packed in a 16-bit frame
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16-bit data packed in a 32-bit frame
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24-bit data packed in a 32-bit frame
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32-bit data packed in a 32-bit frame
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S is shown in .
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S interface when the I
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S mode. One is linked to the clock generator
DocID029473 Rev 3
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S capability is enabled (by setting
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S is configured in master
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S configuration register
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S mode. Likewise, the
RM0430
, where
S