ST STM32F413 Reference Manual page 1157

RM0430
31 30 29
Res. Res. Res. Res.
15 14 13
PTCTL PPWR
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Bits 31:19 Reserved, must be kept at reset value.
Bits 18:17 PSPD: Port speed
Indicates the speed of the device attached to this port.
01: Full speed
10: Low speed
11: Reserved
Bits 16:13 PTCTL: Port test control
The application writes a nonzero value to this field to put the port into a Test mode, and the
corresponding pattern is signaled on the port.
0000: Test mode disabled
0001: Test_J mode
0010: Test_K mode
0011: Test_SE0_NAK mode
0100: Test_Packet mode
0101: Test_Force_Enable
Others: Reserved
Bit 12 PPWR: Port power
The application uses this field to control power to this port, and the core clears this bit on an
overcurrent condition.
0: Power off
1: Power on
Bits 11:10 PLSTS: Port line status
Indicates the current logic level USB data lines
Bit 10: Logic level of OTG_DP
Bit 11: Logic level of OTG_DM
Bit 9 Reserved, must be kept at reset value.
Bit 8 PRST: Port reset
When the application sets this bit, a reset sequence is started on this port. The application
must time the reset period and clear this bit after the reset sequence is complete.
0: Port not in reset
1: Port in reset
The application must leave this bit set for a minimum duration of at least 10 ms to start a
reset on the port. The application can leave it set for another 10 ms in addition to the
required minimum duration, before clearing the bit, even though there is no maximum limit
set by the USB standard.
High speed: 50 ms
Full speed/Low speed: 10 ms
28 27 26 25
Res. Res. Res.
12 11 10 9
PLSTS Res.
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DocID029473 Rev 3
USB on-the-go full-speed (OTG_FS)
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
POC
PRST PSUSP PRES
CHNG
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20 19 18 17
Res. Res. PSPD
r
4 3 2 1
PEN
POCA PENA PCDET PCSTS
CHNG
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16
PTCTL
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0
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