Interrupt Clear Register (Fmpi2C_Icr) - ST STM32F413 Reference Manual

RM0430
Bit 2 RXNE: Receive data register not empty (receivers)
This bit is set by hardware when the received data is copied into the FMPI2C_RXDR register,
and is ready to be read. It is cleared when FMPI2C_RXDR is read.
Note: This bit is cleared by hardware when PE=0.
Bit 1 TXIS: Transmit interrupt status (transmitters)
This bit is set by hardware when the FMPI2C_TXDR register is empty and the data to be
transmitted must be written in the FMPI2C_TXDR register. It is cleared when the next data to
be sent is written in the FMPI2C_TXDR register.
This bit can be written to '1' by software when NOSTRETCH=1 only, in order to generate a
TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1).
Note: This bit is cleared by hardware when PE=0.
Bit 0 TXE: Transmit data register empty (transmitters)
This bit is set by hardware when the FMPI2C_TXDR register is empty. It is cleared when the
next data to be sent is written in the FMPI2C_TXDR register.
This bit can be written to '1' by software in order to flush the transmit data register
FMPI2C_TXDR.
Note: This bit is set by hardware when PE=0.
26.7.8

Interrupt clear register (FMPI2C_ICR)

Address offset: 0x1C
Reset value: 0x0000 0000
Access: No wait states
31 30 29
Res. Res. Res. Res.
15 14 13
ALERT
Res. Res.
CF OUTCF
w
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 ALERTCF: Alert flag clear
Writing 1 to this bit clears the ALERT flag in the FMPI2C_ISR register.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 12 TIMOUTCF: Timeout detection flag clear
Writing 1 to this bit clears the TIMEOUT flag in the FMPI2C_ISR register.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 11 PECCF: PEC Error flag clear
Writing 1 to this bit clears the PECERR flag in the FMPI2C_ISR register.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
28 27 26 25
Res. Res. Res.
12 11 10 9
TIM ARLO
PECCF OVRCF
CF
w w w w
Please refer to Section 26.3: FMPI2C
Please refer to Section 26.3: FMPI2C
Please refer to Section 26.3: FMPI2C
24 23 22
Res. Res. Res.
8 7 6
BERR
Res. Res.
CF
w
implementation.
implementation.
implementation.
DocID029473 Rev 3
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
STOP NACK ADDR
Res.
CF CF CF
w w w
17 16
Res. Res.
1 0
Res. Res.
815/1284
819