Dma Features - ST STM32F413 Reference Manual

RM0430
Overrun flag (OVR)
This flag is set when data are received and the previous data have not yet been read from
the SPIx_DR register. As a result, the incoming data are lost. An interrupt may be generated
if the ERRIE bit is set in the SPIx_CR2 register.
In this case, the receive buffer contents are not updated with the newly received data from
the transmitter device. A read operation to the SPIx_DR register returns the previous
correctly received data. All other subsequently transmitted half-words are lost.
Clearing the OVR bit is done by a read operation on the SPIx_DR register followed by a
read access to the SPIx_SR register.
Frame error flag (FRE)
This flag can be set by hardware only if the I
external master is changing the WS line while the slave is not expecting this change. If the
synchronization is lost, the following steps are required to recover from this state and
resynchronize the external master device with the I
1. Disable the I
2. Enable it again when the correct level is detected on the WS line (WS line is high in I
mode or low for MSB- or LSB-justified or PCM modes.
Desynchronization between master and slave devices may be due to noisy environment on
the SCK communication clock or on the WS frame synchronization line. An error interrupt
can be generated if the ERRIE bit is set. The desynchronization flag (FRE) is cleared by
software when the status register is read.
2
29.6.8 I S interrupts
Table 161
Transmit buffer empty flag
Receive buffer not empty flag
Overrun error
Underrun error
Frame error flag
29.6.9

DMA features

2
In I S mode, the DMA works in exactly the same way as it does in SPI mode. There is no
difference except that the CRC feature is not available in I
transfer protection system.
2
S.
2
provides the list of I S interrupts.
Table 161. I
Interrupt event
DocID029473 Rev 3
Serial peripheral interface/ inter-IC sound (SPI/I2S)
2
S is configured in Slave mode. It is set if the
2
S slave device:
2
S interrupt requests
Event flag
TXE
RXNE
OVR
UDR
FRE
2
Enable control bit
TXEIE
RXNEIE
ERRIE
S mode since there is no data
2
S
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