Adc Watchdog Higher Threshold Register (Adc_Htr) - ST STM32F413 Reference Manual

RM0430
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x
13.12.7

ADC watchdog higher threshold register (ADC_HTR)

Address offset: 0x24
Reset value: 0x0000 0FFF
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 HT[11:0]: Analog watchdog higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Note: The software can write to these registers when an ADC conversion is ongoing. The
programmed value will be effective when the next conversion is complete. Writing to this
register is performed with a write delay that can create uncertainty on the effective time at
which the new value is programmed.
13.12.8 ADC watchdog lower threshold register (ADC_LTR)
Address offset: 0x28
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 LT[11:0]: Analog watchdog lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Note: The software can write to these registers when an ADC conversion is ongoing. The
programmed value will be effective when the next conversion is complete. Writing to this
register is performed with a write delay that can create uncertainty on the effective time at
which the new value is programmed.
These bits are written by software to define the offset to be subtracted from the raw
converted data when converting injected channels. The conversion result can be read from
in the ADC_JDRx registers.
27 26 25
Res. Res. Res.
11 10 9
rw rw rw
27 26 25
Res. Res. Res.
11 10 9
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
HT[11:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
LT[11:0]
rw rw rw
DocID029473 Rev 3
Analog-to-digital converter (ADC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
17 16
Res. Res.
1 0
rw rw
17 16
Res. Res.
1 0
rw rw
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