Data Transfer - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

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Data transfer

The data transfer is managed through transmit and receive data registers and a shift

The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is

received), the shift register is copied into FMPI2C_RXDR register if it is empty (RXNE=0). If

RXNE=1, meaning that the previous received data byte has not yet been read, the SCL line

is stretched low until FMPI2C_RXDR is read. The stretch is inserted between the 8th and

9th SCL pulse (before the Acknowledge pulse).

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface

Figure 246. Data reception

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