Error Conditions - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

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Fast-mode Plus Inter-integrated circuit (FMPI2C) interface

Error conditions

The following are the error conditions which may cause communication to fail.

Bus error (BERR)

A bus error is detected when a START or a STOP condition is detected and is not located

after a multiple of 9 SCL clock pulses. A START or a STOP condition is detected when a

SDA edge occurs while SCL is high.

The bus error flag is set only if the FMPI2C is involved in the transfer as master or

addressed slave (i.e not during the address phase in slave mode).

Figure 271. Bus transfer diagrams for SMBus master receiver

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