ST STM32F413 Reference Manual page 1090

Controller area network (bxCAN)
CAN filter FIFO assignment register (CAN_FFA1R)
Address offset: 0x214
Reset value: 0x0000 0000
This register can be written only when the filter initialization mode is set (FINIT=1) in the
CAN_FMR register.
31 30 29
Res. Res. Res. Res.
15 14 13
FFA15 FFA14 FFA13 FFA12
rw rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:0 FFAx
Note: Bits 27:14 are available for dual CAN peripheral configuration and are reserved for
CAN filter activation register (CAN_FA1R)
Address offset: 0x21C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
FACT1 FACT1 FACT1 FACT1
5 4 3
rw rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:0 FACTx
The software sets this bit to activate Filter x. To modify the Filter x registers (CAN_FxR[0:7]),
the FACTx bit must be cleared or the FINIT bit of the CAN_FMR register must be set.
0: Filter x is not active
1: Filter x is active
Note: Bits 27:14 are available for dual CAN peripheral configuration and are reserved for
1090/1284
28 27 26 25
FFA27 FFA26 FFA25
rw rw rw
12 11 10 9
FFA11 FFA10 FFA9
rw rw rw rw
:
Filter FIFO assignment for filter x
The message passing through this filter will be stored in the specified FIFO.
0: Filter assigned to FIFO 0
1: Filter assigned to FIFO 1
single CAN peripheral configuration.
28 27 26 25
FACT2 FACT2 FACT2
7 6 5
rw rw rw
12 11 10 9
FACT1 FACT1
FACT9 FACT8 FACT7 FACT6 FACT5 FACT4 FACT3 FACT2 FACT1 FACT0
2 1 0
rw rw rw rw
:
Filter active
single CAN peripheral configuration.
24 23 22
FFA24 FFA23 FFA22
rw rw rw
8 7 6
FFA8 FFA7 FFA6
rw rw rw
24 23 22
FACT2 FACT2 FACT2
4 3 2
rw rw rw
8 7 6
rw rw rw
DocID029473 Rev 3
21 20 19 18
FFA21 FFA20 FFA19 FFA18
rw rw rw rw
5 4 3
FFA5 FFA4 FFA3 FFA2
rw rw rw rw
21 20 19 18
FACT2 FACT2 FACT1 FACT1
1 0 9
rw rw rw rw
5 4 3
rw rw rw rw
RM0430
17 16
FFA17 FFA16
rw rw
2 1 0
FFA1 FFA0
rw rw
17 16
FACT1 FACT1
8 7 6
rw rw
2 1 0
rw rw