Advanced encryption standard hardware accelerator (AES)
Suspend mode during Payload phase: the user must respect the following steps:
•
Before interrupting the current message:
a)
b)
c)
d)
Note:
AES_IVx registers are modified during payload phase.
e)
f)
•
To resume:
g)
h)
i)
j)
k)
Suspend mode in GMAC
GMAC is exactly the same as GCM algorithm except: only Header phase can be interrupt.
24.7
AES cipher message authentication code mode
CMAC allows to authenticate the plaintext, generating the corresponding TAG. The
message is composed only by the header phase and the tag phase. The CCM standard
(RFC 3610 Counter with CBC-MAC (CCM) dated September 2003) defines particular
encoding rules for the first authentication block (called B0 in the standard). In particular, the
first block includes flags, a nonce and the payload length expressed in bytes.
a)
b)
c)
•
CMAC header phase:
692/1284
Read 4 times the AES_DOUTR register.
Make sure that busy flag is set to 0 (only in encryption mode, not necessary in
decryption mode).
Save AES_SUSPxR registers in the memory.
Save AES initialization vector registers AES_IVx in the memory.
Disable AES processor by setting EN i n AES_CR to 0.
Save the current AES configuration in the memory (except AES initialization
vector values)
Make sure that AES processor is disabled by reading EN in AES_CR.
Write back AES_SUSPxR registers into their corresponding suspend registers.
Write back AES_IVx registers into their AES initialization vectors.
Re-configure AES with the initial setting values in CR register and key registers.
Enable the AES processor by setting EN bit in AES_CR register.
Make sure that the AES processor is disabled by clearing EN (AES_CR) and that
AES operating mode is different than mode 2 (key derivation) and mode 4 (key
derivation + decryption)
Select CMAC chaining mode by programming CHMOD bits[2:0] = 100 in
AES_CR.
Initialize key registers (128 / 256 bits) in AES_KEYRx and IV with zero values in
AES_IVRx
DocID029473 Rev 3
(CMAC)
RM0430
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