Otg Host Port Control And Status Register (Otg_Hprt) - ST STM32F413 Reference Manual

USB on-the-go full-speed (OTG_FS)
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 HAINT: Channel interrupts
33.15.23 OTG Host all channels interrupt mask register
(OTG_HAINTMSK)
Address offset: 0x418
Reset value: 0x0000 0000
The host all channel interrupt mask register works with the host all channel interrupt register
to interrupt the application when an event occurs on a channel. There is one interrupt mask
bit per channel, up to a maximum of 16 bits.
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 HAINTM: Channel interrupt mask
0: Masked interrupt
1: Unmasked interrupt
One bit per channel: Bit 0 for channel 0, bit 15 for channel 15

33.15.24 OTG Host port control and status register (OTG_HPRT)

Address offset: 0x440
Reset value: 0x0000 0000
This register is available only in host mode. Currently, the OTG host supports only one port.
A single register holds USB port-related information such as USB reset, enable, suspend,
resume, connect status, and test mode for each port. It is shown in
bits in this register can trigger an interrupt to the application through the host port interrupt
bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a Port Interrupt, the
application must read this register and clear the bit that caused the interrupt. For the rc_w1
bits, the application must write a 1 to the bit to clear the interrupt.
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One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15
28 27 26 25
Res. Res. Res.
12 11 10 9
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DocID029473 Rev 3
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
HAINTM
rw rw rw rw
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
rw rw rw rw
Figure 388. The rc_w1
RM0430
16
Res.
0
rw