Advertisement
RM0430
19.5.2
TIM10/11/13/14 Interrupt enable register (TIMx_DIER)
Address offset: 0x0C
Reset value: 0x0000
15
14
13
Res.
Res.
Res.
Res.
Bits 15:2
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
Bit 0 UIE: Update interrupt enable
19.5.3
TIM10/11/13/14 status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
15
14
13
Res.
Res.
Res.
Res.
Bits 15:10
Reserved, must be kept at reset value.
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to '0'.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:2
Reserved, must be kept at reset value.
12
11
10
9
Res.
Res.
Res.
Reserved, must be kept at reset value.
0: CC1 interrupt disabled
1: CC1 interrupt enabled
0: Update interrupt disabled
1: Update interrupt enabled
12
11
10
9
Res.
Res.
CC1OF
rc_w0
General-purpose timers (TIM9 to TIM14)
8
7
6
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
DocID029473 Rev 3
5
4
3
2
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
1
0
CC1IE
UIE
rw
rw
1
0
CC1IF
UIF
rc_w0
rc_w0
621/1284
630
Advertisement
Need help?
Do you have a question about the STM32F413 and is the answer not in the manual?
Questions and answers