Tim2 Option Register (Tim2_Or) - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

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Configure the corresponding DMA channel as follows:

Configure the DCR register by configuring the DBA and DBL bit fields as follows:

DBL = 3 transfers, DBA = 0xE.

Enable the TIMx update DMA request (set the UDE bit in the DIER register).

Enable the DMA channel

This example is for the case where every CCRx register to be updated once. If every CCRx

take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and

data6. The data is transferred to the CCRx registers as follows: on the first update DMA

request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to

CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is

transferred to CCR3 and data6 is transferred to CCR4.

TIM2 option register (TIM2_OR)

Address offset: 0x50

Reset value: 0x0000

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:10 ITR1_RMP: Internal trigger 1 remap

Set and cleared by software.

00: TIM8_TRGOUT

01: Reserved

10: OTG FS SOF is connected to the TIM2_ITR1 input

11: OTG HS SOF is connected to the TIM2_ITR1 input

Bits 9:0 Reserved, must be kept at reset value.

DMA channel peripheral address is the DMAR register address

DMA channel memory address is the address of the buffer in the RAM containing

the data to be transferred by DMA into CCRx registers.

Number of data to transfer = 3 (See note below).

Circular mode disabled.

DocID029473 Rev 3

General-purpose timers (TIM2 to TIM5)