Rng Data Register (Rng_Dr) - ST STM32F413 Reference Manual

True Random Number Generator (RNG)
Bits 31:7 Reserved, must be kept at reset value
Bit 6 SEIS: Seed error interrupt status
This bit is set at the same time as SECS. It is cleared by writing it to '0'.
An interrupt is pending if IE = '1' in the RNG_CR register.
Bit 5 CEIS: Clock error interrupt status
This bit is set at the same time as CECS. It is cleared by writing it to '0'.
An interrupt is pending if IE = '1' in the RNG_CR register.
Bits 4:3 Reserved, must be kept at reset value
Bit 2 SECS: Seed error current status
Bit 1 CECS: Clock error current status
Bit 0 DRDY: Data Ready
Once the RNG_DR register has been read, this bit returns to '0' until a new random value is
generated.
If IE='1' in the RNG_CR register, an interrupt is generated when DRDY='1'.
16.8.3

RNG data register (RNG_DR)

Address offset: 0x008
Reset value: 0x0000 0000
The RNG_DR register is a read-only register that delivers a 32-bit random value when read.
After being read this register delivers a new random value after 42 periods of RNG clock if
the output FIFO is empty.
The content of this register is valid when DRDY='1', even if RNGEN='0'.
31 30 29
r r r
15 14 13
r r r
Bits 31:0 RNDATA[31:0]: Random data
32-bit random data which are valid when DRDY='1'. When DRDY='0' RNDATA value is zero.
450/1284
0: No faulty sequence detected
1: At least one faulty sequence has been detected. See SECS bit description for details.
0: The RNG clock is correct (fRNGCLK > fHCLK/16)
1: The RNG clock has been detected too slow (fRNGCLK < fHCLK/16)
0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a
faulty sequence was detected and the situation has been recovered.
1: One of the noise source has provided more than 64 consecutive bits at a constant value
("0" or "1"), or more than 32 consecutive occurrence of two bits patterns ("01" or "10")
0: The RNG clock is correct (fRNGCLK> fHCLK/16). If the CEIS bit is set, this means that a
slow clock was detected and the situation has been recovered.
1: The RNG clock is too slow (fRNGCLK< fHCLK/16).
0: The RNG_DR register is not yet valid, no random data is available.
1: The RNG_DR register contains valid random data.
28 27 26 25
r r r r
12 11 10 9
r r r r
24 23 22
RNDATA[31:16]
r r r
8 7 6
RNDATA[15:0]
r r r
DocID029473 Rev 3
21 20 19 18
r r r r
5 4 3 2
r r r r
RM0430
17 16
r r
1 0
r r