Rcc Dedicated Clocks Configuration Register (Rcc_Dckcfgr2) - ST STM32F413 Reference Manual

RM0430
6.3.29

RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR2)

Address offset: 0x94
Reset value: 0x0000 0000
This register allows to enable or disable the clock gating for the specified IPs.
31 30 29
LPTIMER1
Res.
SEL
rw
15 14 13
Res. Res. Res.
Bits 31:30 LPTIMER1SEL: LPTIMER1 kernel clock source selection.
Bit:29 Reserved, must be kept at reset value.
Bit 28 CKSDIOSEL: SDIO clock selection.
Bit 27 CK48MSEL: SDIO/USBFS clock selection.
Bits 26:24 Reserved, must be kept at reset value.
Bits 23:22 I2CFMP1SEL[1:0]: I2CFMP1 kernel clock source selection
Bits 21: 0 Reserved, must be kept at reset value.
28 27 26
SDIO CK48M
Res.
SEL SEL
rw rw
12 11 10
Res. Res. Res. Res.
00: APB clock selected as LPTIMER1 clock
01: HSI clock selected as LPTIMER1 clock
10: LSI clock selected as LPTIMER1 clock
11: LSE clock selected as LPTIMER1 clock
0: CK_48MHz (see CK48MSEL bit definition)
1: clock system
0: f( )
PLL_Q
1: f( )
PLLI2S_Q
00: APB clock selected as I2CFMP1 clock
01: System clock selected as I2CFMP1 clock
10: HSI clock selected as I2CFMP1 clock
11: APB clock selected as I2CFMP1 (same as "00")
Reset and clock control (RCC) for STM32F413/423
25 24 23 22
I2CFMP1
SEL[1:0]
rw
9 8 7 6
Res. Res. Res.
DocID029473 Rev 3
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
17 16
Res. Res.
1 0
Res. Res.
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