Adc Sample Time Register 1 (Adc_Smpr1) - ST STM32F413 Reference Manual

RM0430
Bit 11 ALIGN: Data alignment
Bit 10 EOCS: End of conversion selection
Bit 9 DDS: DMA disable selection (for single ADC mode)
Bit 8 DMA: Direct memory access mode (for single ADC mode)
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 CONT: Continuous conversion
Bit 0 ADON: A/D Converter ON / OFF
Note: 0: Disable ADC conversion and go to power down mode
13.12.4

ADC sample time register 1 (ADC_SMPR1)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
SMP15_0 SMP14[2:0]
rw rw rw
This bit is set and cleared by software. Refer to
0: Right alignment
1: Left alignment
This bit is set and cleared by software.
0: The EOC bit is set at the end of each sequence of regular conversions. Overrun detection
is enabled only if DMA=1.
1: The EOC bit is set at the end of each regular conversion. Overrun detection is enabled.
This bit is set and cleared by software.
0: No new DMA request is issued after the last transfer (as configured in the DMA controller)
1: DMA requests are issued as long as data are converted and DMA=1
This bit is set and cleared by software. Refer to the DMA controller chapter for more details.
0: DMA mode disabled
1: DMA mode enabled
This bit is set and cleared by software. If it is set, conversion takes place continuously until it
is cleared.
0: Single conversion mode
1: Continuous conversion mode
This bit is set and cleared by software.
1: Enable ADC
28 27 26 25
Res. Res. SMP18[2:0]
rw rw
12 11 10 9
SMP13[2:0]
rw rw rw rw
24 23 22
SMP17[2:0]
rw rw rw
8 7 6
SMP12[2:0]
rw rw rw
DocID029473 Rev 3
Analog-to-digital converter (ADC)
Figure 63 and Figure 64.
21 20 19
SMP16[2:0]
rw rw rw
5 4 3
SMP11[2:0]
rw rw rw
18 17 16
SMP15[2:1]
rw rw rw
2 1 0
SMP10[2:0]
rw rw rw
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