ST STM32F413 Reference Manual page 173

RM0430
Bit 22 PLLI2SSRC: PLLI2S entry clock source
Bits 21:15 Reserved, must be kept at reset value.
Bits 14:6 PLLI2SN[8:0]: PLLI2S multiplication factor for VCO
Caution: The software has to set these bits correctly to ensure that the VCO output frequency
000000000: PLLI2SN = 0, wrong configuration
000000001: PLLI2SN = 1, wrong configuration
...
001100010: PLLI2SN = 50
...
001100011: PLLI2SN = 99
001100100: PLLI2SN = 100
001100101: PLLI2SN = 101
001100110: PLLI2SN = 102
...
110110000: PLLI2SN = 432
110110000: PLLI2SN = 433, wrong configuration
...
111111111: PLLI2SN = 511, wrong configuration
Note: Between 50 and 99 multiplication factors are possible for VCO input frequency higher
Bits 5:0 PLLI2SM[5:0]: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
Caution: The software has to set these bits correctly to ensure that the VCO input frequency
000000: PLLI2SM = 0, wrong configuration
000001: PLLI2SM = 1, wrong configuration...
000010: PLLI2SM = 2
000011: PLLI2SM = 3
000100: PLLI2SM = 4
.......
111110: PLLI2SM = 62
111111: PLLI2SM = 63
Set and cleared by software to select PLLI2S clock source. This bit can be written only when
PLLI2S is disabled.
0: HSE or HSI depending on PLLSRC of PLLCFGR
1: external AFI clock (CK_I2S_EXT) selected as PLL clock entry
Set and cleared by software to control the multiplication factor of the VCO. These bits can be
written only when the PLLI2S is disabled. Only half-word and word accesses are allowed to
write these bits.
is between 100 and 432 MHz. With VCO input frequency ranges from 1 to 2 MHz
(refer to Figure 14
(RCC_PLLCFGR))
VCO output frequency = VCO input frequency × PLLI2SN with 50 ≤ PLLI2SN ≤ 432
than 1 MHz. However care must be taken to fulfill the minimum VCO output frequency
as specified above.
Set and cleared by software to divide the PLL and PLLI2S input clock before the VCO.
These bits can be written only when the PLL and PLLI2S are disabled.
ranges from 1 to 2 MHz.It is recommended to select a frequency of 2 MHz to limit
PLL jitter.
VCO input frequency = PLL input clock frequency / PLLI2SM with 2 ≤ PLLI2SM ≤ 63
Reset and clock control (RCC) for STM32F413/423
and divider factor M of the
DocID029473 Rev 3
RCC PLL configuration register
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