Quadspi Polling Status Mask Register (Quadspi _Psmkr) - ST STM32F413 Reference Manual

Quad-SPI interface (QUADSPI)
12.5.10

QUADSPI polling status mask register (QUADSPI _PSMKR)

Address offset: 0x0024
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31: 0 MASK[31: 0]: Status mask
12.5.11 QUADSPI polling status match register (QUADSPI _PSMAR)
Address offset: 0x0028
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31: 0 MATCH[31: 0]: Status match
330/1284
27 26 25 24
rw rw rw rw
11 10 9 8
rw rw rw rw
Mask to be applied to the status bytes received in polling mode.
For bit n:
0: Bit n of the data received in automatic polling mode is masked and its value is not
considered in the matching logic
1: Bit n of the data received in automatic polling mode is unmasked and its value is
considered in the matching logic
This field can be written only when BUSY = 0.
27 26 25 24
MATCH[31:16]
rw rw rw rw
11 10 9 8
rw rw rw rw
Value to be compared with the masked status register to get a match.
This field can be written only when BUSY = 0.
DocID029473 Rev 3
23 22 21
MASK[31:16]
rw rw rw
7 6 5
MASK[15:0]
rw rw rw
23 22 21
rw rw rw
7 6 5
MATCH[15:0]
rw rw rw
20 19 18 17
rw rw rw rw
4 3 2 1
rw rw rw rw
20 19 18 17
rw rw rw rw
4 3 2 1
rw rw rw rw
RM0430
16
rw
0
rw
16
rw
0
rw