Timer Synchronization (Tim9/12) - ST STM32F413 Reference Manual

General-purpose timers (TIM9 to TIM14)
19.3.12

Timer synchronization (TIM9/12)

The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 18.3.15: Timer synchronization
19.3.13 Debug mode
When the microcontroller enters debug mode (Cortex
counter either continues to work normally or stops, depending on DBG_TIMx_STOP
configuration bit in DBG module. For more details, refer to
for timers, watchdog, bxCAN and
19.4 TIM9 and TIM12 registers
Refer to
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
19.4.1 TIM9/12 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD: Clock division
Bit 7 ARPE: Auto-reload preload enable
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One-pulse mode
606/1284
Section 1.1 on page 51
12 11 10 9
Res. Res. CKD[1:0]
rw
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (TIx),
00: t = t
DTS CK_INT
01: t = 2 × t
DTS CK_INT
10: t = 4 × t
DTS CK_INT
11: Reserved
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
0: Counter is not stopped on the update event
1: Counter stops counting on the next update event (clearing the CEN bit).
for details.
I2C.
for a list of abbreviations used in register descriptions.
8 7 6
ARPE Res.
rw rw
DocID029473 Rev 3
®
-M4 with FPU core halted), the TIMx
Section 33.16.2: Debug support
5 4 3
Res. Res. OPM URS
rw rw
RM0430
2 1 0
UDIS CEN
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