Tim5 Option Register (Tim5_Or) - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

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General-purpose timers (TIM2 to TIM5)

TIM5 option register (TIM5_OR)

Address offset: 0x50

Reset value: 0x0000

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:6 TI4_RMP: Timer Input 4 remap

Set and cleared by software.

00: TIM5 Channel4 is connected to the GPIO: Refer to the Alternate function mapping table

in the datasheets.

01: the LSI internal clock is connected to the TIM5_CH4 input for calibration purposes

10: the LSE internal clock is connected to the TIM5_CH4 input for calibration purposes

11: the RTC wakeup interrupt is connected to TIM5_CH4 input for calibration purposes.

Wakeup interrupt should be enabled.

Bits 5:0 Reserved, must be kept at reset value.

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