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Sdio Registers - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus
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RM0430
SDIOCLK are frozen, the APB2 interface is still alive. The FIFO can thus be filled or emptied
even if flow control is activated.
To enable HW flow control, the SDIO_CLKCR[14] register bit must be set to 1. After reset
Flow Control is disabled.
31.8

SDIO registers

The device communicates to the system via 32-bit-wide control registers accessible via
APB2.
31.8.1
SDIO power control register (SDIO_POWER)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
[1:0] PWRCTRL: Power supply control bits.
These bits are used to define the current functional state of the card clock:
00: Power-off: the clock to card is stopped.
01: Reserved
10: Reserved power-up
11: Power-on: the card is clocked.
Note:
At least seven PCLK2 clock periods are needed between two write accesses to this register.
Note:
After a data write, data cannot be written to this register for three SDIOCLK clock periods
plus two PCLK2 clock periods.
31.8.2
SDIO clock control register (SDIO_CLKCR)
Address offset: 0x04
Reset value: 0x0000 0000
The SDIO_CLKCR register controls the SDIO_CK output clock.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
HWFC
NEGE
Res.
_EN
DGE
rw
rw
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
WID
BYPAS
PWRS
BUS
S
AV
rw
rw
rw
rw
DocID029473 Rev 3
Secure digital input/output interface (SDIO)
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
CLKEN
rw
rw
rw
rw
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
20
19
18
Res.
Res.
Res.
5
4
3
2
CLKDIV
rw
rw
rw
17
16
Res.
Res.
1
0
PWRCTRL
rw
rw
17
16
Res.
Res.
1
0
rw
rw
1035/1284
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