ST STM32F413 Reference Manual page 212

Direct memory access controller (DMA)
•
Each stream also supports software trigger for memory-to-memory transfers (only
available for the DMA2 controller)
•
Each stream request can be selected via among up to 16 possible channel requests.
This selection is software-configurable and allows several peripherals to initiate DMA
requests
•
The number of data items to be transferred can be managed either by the DMA
controller or by the peripheral:
–
–
•
Independent source and destination transfer width (byte, half-word, word): when the
data widths of the source and destination are not equal, the DMA automatically
packs/unpacks the necessary transfers to optimize the bandwidth. This feature is only
available in FIFO mode
•
Incrementing or non-incrementing addressing for source and destination
• Supports incremental burst transfers of 4, 8 or 16 beats. The size of the burst is
software-configurable, usually equal to half the FIFO size of the peripheral
•
Each stream supports circular buffer management
•
5 event flags (DMA Half Transfer, DMA Transfer complete, DMA Transfer Error, DMA
FIFO Error, Direct Mode Error) logically ORed together in a single interrupt request for
each stream
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DMA flow controller: the number of data items to be transferred is software-
programmable from 1 to 65535
Peripheral flow controller: the number of data items to be transferred is unknown
and controlled by the source or the destination peripheral that signals the end of
the transfer by hardware
DocID029473 Rev 3
RM0430