Rising Trigger Selection Register (Exti_Rtsr) - ST STM32F413 Reference Manual

Interrupts and events
10.3.3

Rising trigger selection register (EXTI_RTSR)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
TR15 TR14 TR13 TR12
rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:21 TR[22:21]: Rising trigger event configuration bit of line x
Bits 20:19 Reserved, must be kept at reset value.
Bits 18:0 TR[18:0: Rising trigger event configuration bit of line x
Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines.
If a rising edge occurs on the external interrupt line while writing to the EXTI_RTSR register,
the pending bit is be set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
256/1284
28 27 26 25
Res. Res. Res.
12 11 10 9
TR11 TR10 TR9
rw rw rw rw
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
24 23 22
Res. Res. TR22
rw
8 7 6
TR8 TR7 TR6
rw rw rw
DocID029473 Rev 3
21 20 19 18
TR21 Res. Res. TR18
rw rw
5 4 3 2
TR5 TR4 TR3 TR2
rw rw rw rw
RM0430
17 16
TR17 TR16
rw rw
1 0
TR1 TR0
rw rw