Otg Reset Register (Otg_Grstctl) - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

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Bit 6 PHYSEL: Full Speed serial transceiver select

This bit is always 1 with read-only access.

Bits 5:3 Reserved, must be kept at reset value.

Bits 2:0 TOCAL: FS timeout calibration

The number of PHY clocks that the application programs in this field is added to the full-

speed interpacket timeout duration in the core to account for any additional delays

introduced by the PHY. This can be required, because the delay introduced by the PHY in

generating the line state condition can vary from one PHY to another.

The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The

application must program this field based on the speed of enumeration. The number of bit

times added per PHY clock is 0.25 bit times.

OTG reset register (OTG_GRSTCTL)

Address offset: 0x10

Reset value: 0x8000 0000

The application uses this register to reset various hardware features inside the core.

AHB frequency range (MHz)

DocID029473 Rev 3

Table 210. TRDT values(FS)

USB on-the-go full-speed (OTG_FS)

TRDT minimum value

FCRST PSRST CSRST