Debug Mode - ST STM32F413 Reference Manual

Window watchdog (WWDG)
As an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3
and T[5:0] is set to 63:
Refer to the datasheets for the minimum and maximum values of the t

23.5

Debug mode

When the microcontroller enters debug mode (Cortex
WWDG counter either continues to work normally or stops, depending on
DBG_WWDG_STOP configuration bit in DBG module. For more details, refer to
Section 33.16.2: Debug support for timers, watchdog, bxCAN and
676/1284
⁄
t WWDG 1 24000
=
DocID029473 Rev 3
3
× × × (
4096 2 63 1
+
®
-M4 with FPU core halted), the
RM0430
)
21.85 ms
=
WWDG.
I2C.