ST STM32F413 Reference Manual page 1075

RM0430
Bit 31 LOW2
This bit is set by hardware when more than one mailbox are pending for transmission and
mailbox 2 has the lowest priority.
Bit 30 LOW1
This bit is set by hardware when more than one mailbox are pending for transmission and
mailbox 1 has the lowest priority.
Bit 29 LOW0
This bit is set by hardware when more than one mailbox are pending for transmission and
mailbox 0 has the lowest priority.
Note: The LOW[2:0] bits are set to zero when only one mailbox is pending.
Bit 28 TME2
This bit is set by hardware when no transmit request is pending for mailbox 2.
Bit 27 TME1
This bit is set by hardware when no transmit request is pending for mailbox 1.
Bit 26 TME0
This bit is set by hardware when no transmit request is pending for mailbox 0.
Bits 25:24 CODE[1:0]
In case at least one transmit mailbox is free, the code value is equal to the number of the
next transmit mailbox free.
In case all transmit mailboxes are pending, the code value is equal to the number of the
transmit mailbox with the lowest priority.
Bit 23 ABRQ2
Set by software to abort the transmission request for the corresponding mailbox.
Cleared by hardware when the mailbox becomes empty.
Setting this bit has no effect when the mailbox is not pending for transmission.
Bits 22:20 Reserved, must be kept at reset value.
Bit 19 TERR2
This bit is set when the previous TX failed due to an error.
Bit 18 ALST2
This bit is set when the previous TX failed due to an arbitration lost.
Bit 17 TXOK2
The hardware updates this bit after each transmission attempt.
0: The previous transmission failed
1: The previous transmission was successful
This bit is set by hardware when the transmission request on mailbox 2 has been completed
successfully. Refer to
Bit 16 RQCP2
Set by hardware when the last request (transmit or abort) has been performed.
Cleared by software writing a "1" or by hardware on transmission request (TXRQ2 set in
CAN_TMID2R register).
Clearing this bit clears all the status bits (TXOK2, ALST2 and TERR2) for Mailbox 2.
Bit 15 ABRQ1
Set by software to abort the transmission request for the corresponding mailbox.
Cleared by hardware when the mailbox becomes empty.
Setting this bit has no effect when the mailbox is not pending for transmission.
Bits 14:12 Reserved, must be kept at reset value.
:
Lowest priority flag for mailbox 2
:
Lowest priority flag for mailbox 1
:
Lowest priority flag for mailbox 0
:
Transmit mailbox 2 empty
:
Transmit mailbox 1 empty
:
Transmit mailbox 0 empty
:
Mailbox code
:
Abort request for mailbox 2
:
Transmission error of mailbox 2
:
Arbitration lost for mailbox 2
:
Transmission OK of mailbox 2
Figure
:
Request completed mailbox2
:
Abort request for mailbox 1
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