Table 103. Output Control Bit For Standard Ocx Channels - ST STM32F413 Reference Manual

General-purpose timers (TIM2 to TIM5)
Bit 7 CC2NP: Capture/Compare 2 output Polarity.
Bit 6
Bit 5 CC2P: Capture/Compare 2 output Polarity.
Bit 4 CC2E: Capture/Compare 2 output enable.
Bit 3 CC1NP: Capture/Compare 1 output Polarity.
Bit 2
Bit 1 CC1P: Capture/Compare 1 output Polarity.
Bit 0 CC1E: Capture/Compare 1 output enable.
CCxE bit
0
1
Note: The state of the external IO pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.
576/1284
refer to CC1NP description
Reserved, must be kept at reset value.
refer to CC1P description
refer to CC1E description
CC1 channel configured as output:
CC1NP must be kept cleared in this case.
CC1 channel configured as input:
This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P
description.
Reserved, must be kept at reset value.
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).
01: inverted/falling edge
Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).
10: reserved, do not use this configuration.
11: noninverted/both edges
Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external
clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration
must not be used for encoder mode.
CC1 channel configured as output:
0: Off - OC1 is not active
1: On - OC1 signal is output on the corresponding output pin
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled

Table 103. Output control bit for standard OCx channels

OCx output state
Output Disabled (OCx=0, OCx_EN=0)
OCx=OCxREF + Polarity, OCx_EN=1
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