ST STM32F413 Reference Manual page 1073

RM0430
Bit 2 TXFP
This bit controls the transmission order when several mailboxes are pending at the same
time.
0: Priority driven by the identifier of the message
1: Priority driven by the request order (chronologically)
Bit 1 SLEEP
This bit is set by software to request the CAN hardware to enter the Sleep mode. Sleep
mode will be entered as soon as the current CAN activity (transmission or reception of a
CAN frame) has been completed.
This bit is cleared by software to exit Sleep mode.
This bit is cleared by hardware when the AWUM bit is set and a SOF bit is detected on the
CAN Rx signal.
This bit is set after reset - CAN starts in Sleep mode.
Bit 0 INRQ
The software clears this bit to switch the hardware into normal mode. Once 11 consecutive
recessive bits have been monitored on the Rx signal the CAN hardware is synchronized and
ready for transmission and reception. Hardware signals this event by clearing the INAK bit in
the CAN_MSR register.
Software sets this bit to request the CAN hardware to enter initialization mode. Once
software has set the INRQ bit, the CAN hardware waits until the current CAN activity
(transmission or reception) is completed before entering the initialization mode. Hardware
signals this event by setting the INAK bit in the CAN_MSR register.
CAN master status register (CAN_MSR)
Address offset: 0x04
Reset value: 0x0000 0C02
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 RX
Bit 10 SAMP
Bit 9 RXM
Bit 8 TXM
Bits 7:5 Reserved, must be kept at reset value.
:
Transmit FIFO priority
:
Sleep mode request
:
Initialization request
28 27 26 25
Res. Res. Res.
12 11 10 9
RX SAMP RXM
r r r
:
CAN Rx signal
Monitors the actual value of the CAN_RX Pin.
:
Last sample point
The value of RX on the last sample point (current received bit value).
:
Receive mode
The CAN hardware is currently receiver.
:
Transmit mode
The CAN hardware is currently transmitter.
DocID029473 Rev 3
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
TXM Res. Res. Res.
r
Controller area network (bxCAN)
20 19 18
Res. Res. Res.
4 3 2
SLAKI WKUI ERRI
rc_w1 rc_w1 rc_w1
17 16
Res. Res.
1 0
SLAK INAK
r r
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