Digital filter for sigma delta modulators (DFSDM)
15.2
DFSDM main features
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Up to 8 multiplexed input digital serial channels:
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Alternative inputs from up to 8 internal digital parallel channels:
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Adjustable digital signal processing:
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Up to 24-bit output data resolution:
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Signed output data format
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Automatic data offset correction (offset stored in register by user)
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Continuous or single conversion
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Start-of-conversion synchronization with:
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Analog watchdog feature:
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Short-circuit detector to detect saturated analog input values (bottom and top ranges):
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Break generation on analog watchdog event or short-circuit detector event
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Extremes detector:
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DMA may be used to read the conversion data
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Interrupts: end of conversion, overrun, analog watchdog, short-circuit, channel clock
absence
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"regular" or "injected" conversions:
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382/1284
configurable SPI interface to connect various Σ∆ modulators
configurable Manchester coded 1 wire interface support
clock output for Σ∆ modulator(s)
inputs with up to 16 bit resolution
internal sources: memory (CPU/DMA write) data streams
x
Sinc
filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
integrator: oversampling ratio (1..256)
right bit-shifter on final data (0..31 bits)
software trigger
internal timers
external events
start-of-conversion synchronously with first DFSDM filter (DFSDM_FLT0)
low value and high value data threshold registers
own configurable Sinc
input from output data register or from one or more input digital serial channels
continuous monitoring independently from standard conversion
up to 8-bit counter to detect 1..256 consecutive 0's or 1's on input data stream
monitoring continuously each channel (8 serial channel transceiver outputs)
store minimum and maximum values of output data values
refreshed by software
"regular" conversions can be requested at any time or even in continuous mode
without having any impact on the timing of "injected" conversions
DocID029473 Rev 3
x
digital filter (order = 1..3, oversampling ratio = 1..32)
RM0430
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