ST STM32F413 Reference Manual page 931

RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S)
When using 16-bit data extended on 32-bit packet, the first 16 bits (MSB) are the significant
bits, the 16-bit LSB is forced to 0 without any need for software action or DMA request (only
one read/write operation).
The 24-bit and 32-bit data frames need two CPU read or write operations to/from the
SPIx_DR register or two DMA operations if the DMA is preferred for the application. For 24-
bit data frame specifically, the 8 non significant bits are extended to 32 bits with 0-bits (by
hardware).
For all data formats and communication standards, the most significant bit is always sent
first (MSB first).
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The I S interface supports four audio standards, configurable using the I2SSTD[1:0] and
PCMSYNC bits in the SPIx_I2SCFGR register.
2
I S Philips standard
For this standard, the WS signal is used to indicate which channel is being transmitted. It is
activated one CK clock cycle before the first bit (MSB) is available.
2
Figure 318. I S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0)
Data are latched on the falling edge of CK (for the transmitter) and are read on the rising
edge (for the receiver). The WS signal is also latched on the falling edge of CK.
2
Figure 319. I S Philips standard waveforms (24-bit frame with CPOL = 0)
This mode needs two write or read operations to/from the SPIx_DR register.
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