Lptim Counter Register (Lptim_Cnt) - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

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LPTIM counter register (LPTIM_CNT)

Address offset: 0x1C

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 CNT: Counter value

When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may

return unreliable values. So in this case it is necessary to perform two consecutive read accesses

and verify that the two returned values are identical.

It should be noted that for a reliable LPTIM_CNT register read access, two consecutive read

accesses must be performed and compared. A read access can be considered reliable when the

values of the two consecutive read accesses are equal.

LPTIM1 option register (LPTIM1_OPTR)

Address offset: 0x20

Reset value: 0x0000 0000

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 TIM9_ITR1_RMP: TIMER9 input Trigger 1 remap

Set and cleared by software.

TIM3 output trigger

Output channel of LPTIMERS

DocID029473 Rev 3

Low-power timer (LPTIM)