Table 30. Dma1 Request Mapping - ST STM32F413 Reference Manual

RM0430
Peripheral
Stream 0
requests
Channel 0 SPI3_RX
Channel 1 I2C1_RX
Channel 2 TIM4_CH1
Channel 3 I2S3_EXT_RX
Channel 4 UART5_RX
Channel 5 UART8_RX
TIM5_CH3
Channel 6
TIM5_UP
Channel 7 I2CFMP1_RX
Channel 8 -
Peripheral
Stream 0
requests
Channel 0 ADC1
Channel 1 UART9_TX
Channel 2 -
Channel 3 SPI1_RX
Channel 4 SPI4_RX
Channel 5 UART10_RX
Channel 6 TIM1_TRIG
DFSDM1_
Channel 7
FLT0
DFSDM2_
Channel 8
FLT0
Channel 9 -
1. Only available for STM32F423xx.

Table 30. DMA1 request mapping

Stream 1 Stream 2
I2C1_TX SPI3_RX
I2C3_RX TIM7_UP
I2CFMP1_TX I2S3_EXT_RX
TIM2_UP
I2C3_RX
TIM2_CH3
USART3_RX UART4_RX
TIM3_UP
UART7_TX
TIM3_CH4
TIM5_CH4
TIM5_CH1
TIM5_TRIG
TIM6_UP I2C2_RX
- -
Table 31. DMA2 request mapping
Stream 1 Stream 2
TIM8_CH1
SAI1_A TIM8_CH2
TIM8_CH3
- -
- SPI1_TX
DFSDM1_
SPI1_RX
FLT1
SPI4_TX USART1_RX
USART6_RX USART6_RX
TIM1_CH1 TIM1_CH2
TIM8_UP TIM8_CH1
DFSDM2_ DFSDM2_
FLT1 FLT2
- -
DocID029473 Rev 3
Direct memory access controller (DMA)
Stream 3 Stream 4
SPI2_RX SPI2_TX
I2CFMP1_RX TIM7_UP
TIM4_CH2 I2S2_EXT_TX I2S3_EXT_TX
I2S2_EXT_RX I2C3_TX
USART3_TX UART4_TX
TIM3_CH1
UART7_RX
TIM3_TRIG
TIM5_CH4
TIM5_CH2
'TIM5_TRIG
I2C2_RX USART3_TX
- -
Stream 3 Stream 4
SAI1_A ADC1
- SAI1B
SPI5_RX SPI5_TX
DFSDM1_
SPI1_TX
FLT1
SDIO SPI4_RX
SPI4_RX SPI4_TX
TIM1_CH4
TIM1_CH1 TIM1_TRIG
TIM1_COM
TIM8_CH2 TIM8_CH3
DFSDM2_ DFSDM2_
FLT3 FLT0
UART10_RX -
Stream 5 Stream 6
SPI3_TX -
I2C1_RX I2C1_TX
TIM4_UP
TIM2_CH2
TIM2_CH1
TIM2_CH4
USART2_RX USART2_TX
TIM3_CH2 UART8_RX
I2C3_TX TIM5_UP
DAC1 DAC2
- -
Stream 5 Stream 6
TIM1_CH1
SAI1_B TIM1_CH2
TIM1_CH3
- -
(1) (1)
AES_OUT AES_IN
DFSDM1_
SPI1_TX
FLT0
USART1_RX SDIO
SPI5_TX USART6_TX
TIM1_UP TIM1_CH3
SPI5_RX SPI5_TX
DFSDM2_ DFSDM2_
FLT1 FLT2
UART10_TX -
Stream 7
SPI3_TX
I2C1_TX
TIM4_CH3
TIM2_UP
TIM2_CH4
I2CFMP1_TX
TIM3_CH3
USART2_RX
I2C2_TX
UART5_TX
Stream 7
UART9_RX
-
-
QUADSPI
USART1_TX
USART6_TX
UART10_TX
TIM8_CH4
TIM8_TRIG
TIM8_COM
DFSDM2_
FLT3
-
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