ST STM32F413 Reference Manual page 396

Digital filter for sigma delta modulators (DFSDM)
the final output sample (and next samples) from filter will be calculated from later input data.
This final sample then looks a bit in forward - because it is calculated from newer input
samples than the "non-skipped" sample. The final "skipped sample" is converted later
because the skipped input data samples must be replaced by followed input data samples.
The final data buffers behavior (skipped and non-skipped output data buffers comparison)
looks like the non-skipped data stream is a bit delayed - both data buffers will be phase
shifted.
The implementation of clock skipping is based on a block named MCHDLY (multi-channel
delay block) added on the top level of DFSDMs (see
controlled via a MCHDLYCR register (see the
control register
By using MCHDLY block, the DFSDMs can be used for beamforming with up to 6 digital
microphones. In beamforming mode the clock to digital microphones (or sigma-delta
modulators) is provided by DFSDM2 clock output (dfsdm2_ckout signal on
clock output signal is then distributed to (see
• OR gates (to implement pulse skipping by clock masking/gating)
•
Trigger inputs (ETR) of two timers: TIM4 and TIM3 (to define how many pulses will be
skipped)
•
DFSDM1_CKOUT and DFSDM2_CKOUT pins outputs through M1 and M2
multiplexers (to generate output clock signal on DFSDMx pins)
The OR gates are used to skip the input serial clock pulses provided to the DFSDMs in
order to generate a delay on the corresponding input channel.
This clock gating is controlled by two timers (TIM4 and TIM3). Timers are programmed in
one shot mode to generate masking pulse with defined length to gate required number of
clock pulses.
In the Figure
(DFSDM1_CKOUT pin) which can provide either clock output from DFSDM2 or DFSDM1
CKOUT signal. This configuration allows to use for low-power use-cases only one
microphone (MIC1) - while DFSDM2_CKOUT is disabled and DFSDM1_CKOUT enabled
(for example voice detection), and reusing MIC1 for beamforming use cases (when
DFSDM2_CKOUT is enabled).
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(SYSCFG_MCHDLYCR)) where are all MCHDLY control bits.
81, MIC1 receives its serial clock via another clock output pin
DocID029473 Rev 3
Figure 81). This MCHDLY block is
Section 8.2.10: DFSDM Multi-channel delay
Figure 81):
RM0430
Figure 81). This