Sdio Mask Register (Sdio_Mask) - ST STM32F413 Reference Manual

RM0430
Bit 2 CTIMEOUTC: CTIMEOUT flag clear bit
Set by software to clear the CTIMEOUT flag.
0: CTIMEOUT not cleared
1: CTIMEOUT cleared
Bit 1 DCRCFAILC: DCRCFAIL flag clear bit
Set by software to clear the DCRCFAIL flag.
0: DCRCFAIL not cleared
1: DCRCFAIL cleared
Bit 0 CCRCFAILC: CCRCFAIL flag clear bit
Set by software to clear the CCRCFAIL flag.
0: CCRCFAIL not cleared
1: CCRCFAIL cleared
31.8.13

SDIO mask register (SDIO_MASK)

Address offset: 0x3C
Reset value: 0x0000 0000
The interrupt mask register determines which status flags generate an interrupt request by
setting the corresponding bit to 1b.
31 30 29
Res. Res. Res. Res.
15 14 13
RX TX
RX
FIFO FIFO
ACTIE ACTIE
HFIE HEIE
rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 SDIOITIE: SDIO mode interrupt received interrupt enable
Bit 21 RXDAVLIE: Data available in Rx FIFO interrupt enable
Bit 20 TXDAVLIE: Data available in Tx FIFO interrupt enable
28 27 26 25
Res. Res. Res.
12 11 10 9
TX CMD DBCK
Res.
ACTIE ENDIE
rw rw rw
Set and cleared by software to enable/disable the interrupt generated when receiving the
SDIO mode interrupt.
0: SDIO Mode Interrupt Received interrupt disabled
1: SDIO Mode Interrupt Received interrupt enabled
Set and cleared by software to enable/disable the interrupt generated by the presence of
data available in Rx FIFO.
0: Data available in Rx FIFO interrupt disabled
1: Data available in Rx FIFO interrupt enabled
Set and cleared by software to enable/disable the interrupt generated by the presence of
data available in Tx FIFO.
0: Data available in Tx FIFO interrupt disabled
1: Data available in Tx FIFO interrupt enabled
Secure digital input/output interface (SDIO)
24 23 22
SDIO
Res. Res.
ITIE
rw
8 7 6
CMD CMD
DATA
SENT REND
ENDIE
IE IE
rw rw rw
DocID029473 Rev 3
21 20 19
RX
RXD TXD
FIFO
AVLIE AVLIE
EIE
rw rw rw
5 4 3
RX TX
DTIME CTIME
OVERR UNDERR
OUTIE OUTIE
IE IE
rw rw rw
18 17 16
TX RX TX
FIFO FIFO FIFO
EIE FIE FIE
rw rw rw
2 1 0
DCRC CCRC
FAILIE FAILIE
rw rw rw
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