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Table 55. Fsmc_Bcrx Bit Fields - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus
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RM0430
Bit number
31:22
21
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5:4
3:2
1
0
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0

Table 55. FSMC_BCRx bit fields

Bit name
Reserved
0x000
WFDIS
As needed
CCLKEN
As needed
CBURSTRW
0x0 (no effect in asynchronous mode)
CPSIZE
0x0 (no effect in asynchronous mode)
ASYNCWAIT
Set to 1 if the memory supports this feature. Otherwise keep at 0.
EXTMOD
0x1 for mode B, 0x0 for mode 2
WAITEN
0x0 (no effect in asynchronous mode)
WREN
As needed
WAITCFG
Don't care
Reserved
0x0
WAITPOL
Meaningful only if bit 15 is 1
BURSTEN
0x0
Reserved
0x1
FACCEN
0x1
MWID
As needed
MTYP
0x2 (NOR Flash memory)
MUXEN
0x0
MBKEN
0x1
Table 56. FSMC_BTRx bit fields
Bit name
Reserved
0x0
ACCMOD
0x1 if extended mode is set
DATLAT
Don't care
CLKDIV
Don't care
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the access second phase (DATAST HCLK cycles) for
DATAST
read accesses.
ADDHLD
Don't care
Duration of the access first phase (ADDSET HCLK cycles) for read
ADDSET
accesses. Minimum value for ADDSET is 0.
DocID029473 Rev 3
Flexible static memory controller (FSMC)
Value to set
Value to set
277/1284
303

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