Syscfg Configuration Register (Syscfg_Cfgr) - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

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SYSCFG configuration register (SYSCFG_CFGR)

Address offset: 0x2C

Reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 I2CFMP1_SDA

Bit 0 I2CFMP1_SCL

DFSDM Multi-channel delay control register (SYSCFG_MCHDLYCR)

Address offset: 0x30

Reset value: 0x0000 0000

Bits 31:19 Reserved, must be kept at reset value.

Set and cleared by software. When this bit is set, it forces FM+ drive capability on

I2CFMP1_SDA pin selected through GPIO port mode register and GPIO alternate

function selection bits.

Set and cleared by software. When this bit is set, it forces FM+ drive capability on

I2CFMP1_SCL pin selected through GPIO port mode register and GPIO alternate

function selection bits.

DFSDM2_CKOSEL: Source selection for DFSDM2_CKOUT (M2 multiplexer on

Figure 81: Multi-channel delay block for pulse skipping

0: The source for DFSDM2_CKOUT is the CkOut generated by the DFSDM2

1: The source for DFSDM2_CKOUT is the output of M27

DFSDM2_CFG: CkIn source selection for DFSDM2 (M9, M10, M11, M12, M13, M14,

M15, M16 and M2 multiplexers on

0: The source for CkIn[7:0] signals are the pins DFSDM2_CKINy (M[16:9] = 0)

1: The source for CkIn[7:0] signals are provided by the outputs of DM[6:3]

(M16:9] = 1)

DocID029473 Rev 3

System configuration controller (SYSCFG)

Figure 81: Multi-channel delay block for pulse

I2CFMP1_SDA I2CFMP1_SCL