Quadspi Communication Configuration Register (Quadspi_Ccr) - ST STM32F413 Reference Manual

Quad-SPI interface (QUADSPI)
Bits 31:0 DL[31: 0]: Data length
12.5.6

QUADSPI communication configuration register (QUADSPI_CCR)

Address offset: 0x0014
Reset value: 0x0000 0000
31 30 29 28
DDRM DHHC Res. SIOO
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15 14 13 12
ABMODE ADSIZE
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Bit 31 DDRM: Double data rate mode
Bit 30 DHHC: DDR hold
Bit 29 Reserved, must be kept at reset value.
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Number of data to be retrieved (value+1) in indirect and status-polling modes. A value
no greater than 3 (indicating 4 bytes) should be used for status-polling mode.
All 1s in indirect mode means undefined length, where QUADSPI will continue until the
end of memory, as defined by FSIZE.
0x0000_0000: 1 byte is to be transferred
0x0000_0001: 2 bytes are to be transferred
0x0000_0002: 3 bytes are to be transferred
0x0000_0003: 4 bytes are to be transferred
...
0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred
0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred
0xFFFF_FFFF: undefined length -- all bytes until the end of Flash memory (as defined
by FSIZE) are to be transferred. Continue reading indefinitely if FSIZE = 0x1F.
DL[0] is stuck at '1' in dual-flash mode (DFM = 1) even when '0' is written to this bit, thus
assuring that each access transfers an even number of bytes.
This field has no effect when in memory-mapped mode (FMODE = 10).
This field can be written only when BUSY = 0.
27 26 25 24
FMODE[1:0] DMODE
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11 10 9 8
ADMODE IMODE
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This bit sets the DDR mode for the address, alternate byte and data phase:
0: DDR Mode disabled
1: DDR Mode enabled
This field can be written only when BUSY = 0.
Delay the data output by 1/4 of the QUADSPI output clock cycle in DDR mode:
0: Delay the data output using analog delay
1: Delay the data output by 1/4 of a QUADSPI output clock cycle.
This feature is only active in DDR mode.
This field can be written only when BUSY = 0.
DocID029473 Rev 3
23 22 21 20
Res. DCYC[4:0]
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7 6 5 4
INSTRUCTION[7:0]
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RM0430
19 18 17 16
ABSIZE
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3 2 1 0
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