ST STM32F413 Reference Manual page 1172

USB on-the-go full-speed (OTG_FS)
33.15.39 OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK)
Address offset: 0x834
Reset value: 0x0000 0000
This register is used to control the IN endpoint FIFO empty interrupt generation
(TXFE_OTG_DIEPINTx).
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 INEPTXFEM: IN EP Tx FIFO empty interrupt mask bits
33.15.40 OTG device control IN endpoint 0 control register
(OTG_DIEPCTL0)
Address offset: 0x900
Reset value: 0x0000 0000
This section describes the OTG_DIEPCTL0 register for USB_OTG FS. Nonzero control
endpoints use registers for endpoints 1–3.
31 30 29
EPENA EPDIS Res. Res.
rs rs
15 14 13
USBA
Res. Res. Res.
EP
r
1172/1284
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
These bits act as mask bits for OTG_DIEPINTx.
TXFE interrupt one bit per IN endpoint:
Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3
0: Masked interrupt
1: Unmasked interrupt
28 27 26 25
SNAK CNAK
w w rw
12 11 10 9
Res. Res. Res.
DocID029473 Rev 3
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
INEPTXFEM
rw rw rw rw
24 23 22 21
TXFNUM STALL
rw rw rw rs
8 7 6 5
Res. Res. Res. Res.
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
rw rw rw rw
20 19 18 17
NAK
Res. EPTYP
STS
r r r
4 3 2 1
Res. Res. Res.
rw
RM0430
16
Res.
0
rw
16
Res.
0
MPSIZ
rw