Supported Memories And Transactions - ST STM32F413 Reference Manual

Flexible static memory controller (FSMC)
FSMC signal
name
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1:0]
The maximum capacity is 512 Mbits.
PSRAM, 16-bit multiplexed I/Os
FSMC signal
name
CLK
A[25:16]
AD[15:0]
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1:0]
The maximum capacity is 512 Mbits (26 address lines).
11.5.2

Supported memories and transactions

Table 49
transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and
SRAM. The transactions not allowed (or not supported) by the FSMC are shown in gray in
this example.
268/1284
Table 47. Non-multiplexed I/Os PSRAM/SRAM (continued)
I/O
O Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
O
O
O Address valid only for PSRAM input (memory signal name: NADV)
I
O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)
Table 48. 16-Bit multiplexed I/O PSRAM
I/O
O
O
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
I/O
O Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
O
O
O
I
O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)
below shows an example of the supported devices, access modes and
DocID029473 Rev 3
Output enable
Write enable
PSRAM wait input signal to the FSMC
Clock (for synchronous access)
Address bus
A[15:0] and data D[15:0] are multiplexed on the databus)
Output enable
Write enable
Address valid PSRAM input (memory signal name: NADV)
PSRAM wait input signal to the FSMC
Function
Function
RM0430