Sai Registers - ST STM32F413 Reference Manual

Serial audio interface (SAI)
30.17

SAI registers

30.17.1 SAI xConfiguration register 1 (SAI_xCR1) where x is A or B
Address offset: Block A: 0x004
Address offset: Block B: 0x024
Reset value: 0x0000 0040
31 30 29 28
15 14 13 12
OutDri
MONO
v
Reserved
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Bits 31:24 Reserved, always read as 0.
Bit 23:20 MCKDIV[3:0]: Master clock divider. These bits are set and cleared by software.
0000: Divides by 1 the master clock input.
Otherwise, The Master clock frequency is calculated accordingly to the following formula:
MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2)
These bits have no meaning when the audio block is slave.
They have to be configured when the audio block is disabled.
Bit 19 NODIV: No divider. This bit is set and cleared by software.
0: Master Clock divider is enabled
1: No divider used in the clock generator (in this case Master Clock Divider bit has no effect)
Bit 18 Reserved, always read as 0.
Bit 17 DMAEN: DMA enable. This bit is set and cleared by software.
0: DMA is disabled
1: DMA is enabled
Note: In receiver mode, the bits MODE must be configured before setting bit DMAEN to avoid a DMA
request since the audio block is transmitter after reset (default setting)
Bit 16 SAIxEN: Audio block enable where x is A or B. This bit is set by software. It is cleared by hardware,
after disabling it by software (writing the bit low), the audio is completely disabled (waiting for the end
of the current frame).
0: Audio block is disabled
1: Audio block is enabled: this bit can be set only if it is at 0 during the write operation (means the
SAI is completely disabled before being re-enabled).
This bit allows to control the state of the audio block. If it is disabled somewhere in an audio frame,
the on-going transfer will be completed and the cell will be totally disabled at the end of this audio
frame transfer.
Note: When SAIx block is configured as master mode, clock must be present on the input of the SAI
before setting SAIxEN bit.
Bits 15:14 Reserved, always read as 0.
Bit 13 OUTDRIV: Output drive. This bit is set and cleared by software.
0: Audio block output driven when SAIEN is set
1: Audio block output driven immediately after the setting of this bit.
Note: This bit has to be set before enabling the audio block but after the audio block configuration.
978/1284
27 26 25
Reserved
11 10 9
SYNCEN[1:0] CKSTR
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DocID029473 Rev 3
24 23 22
MCKDIV[3:0]
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8 7 6
LSBFIR
DS[2:0]
ST
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21 20 19 18
NODIV
Res.
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5 4 3 2
PRTCFG[1:0]
Res.
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RM0430
17 16
DMAEN SAIxEN
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1 0
MODE[1:0]
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