Dma High Interrupt Status Register (Dma_Hisr) - ST STM32F413 Reference Manual

RM0430
9.5.2

DMA high interrupt status register (DMA_HISR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x=7..4)
Bits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x=7..4)
Bits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x=7..4)
Bits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x=7..4)
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x=7..4)
27 26 25
TCIF7 HTIF7 TEIF7
r r r
11 10 9
TCIF5 HTIF5 TEIF5
r r r
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No transfer complete event on stream x
1: A transfer complete event occurred on stream x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No half transfer event on stream x
1: A half transfer event occurred on stream x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No transfer error on stream x
1: A transfer error occurred on stream x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No Direct mode error on stream x
1: A Direct mode error occurred on stream x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No FIFO error event on stream x
1: A FIFO error event occurred on stream x
Direct memory access controller (DMA)
24 23 22
DMEIF7 Res. FEIF7
r r
8 7 6
DMEIF5 Res. FEIF5
r r
DocID029473 Rev 3
21 20 19
TCIF6 HTIF6 TEIF6 DMEIF6
r r r
5 4 3
TCIF4 HTIF4 TEIF4 DMEIF4
r r r
18 17 16
Res. FEIF6
r r
2 1 0
Res. FEIF4
r r
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