Otg_Fs Control And Status Registers - ST STM32F413 Reference Manual

USB on-the-go full-speed (OTG_FS)
33.14

OTG_FS control and status registers

By reading from and writing to the control and status registers (CSRs) through the AHB
slave interface, the application controls the OTG_FS controller. These registers are 32 bits
wide, and the addresses are 32-bit block aligned. The OTG_FS registers must be accessed
by words (32 bits).
CSRs are classified as follows:
•
Core global registers
•
Host-mode registers
•
Host global registers
•
Host port CSRs
•
Host channel-specific registers
•
Device-mode registers
•
Device global registers
•
Device endpoint-specific registers
•
Power and clock-gating registers
•
Data FIFO (DFIFO) access registers
Only the Core global, Power and clock-gating, Data FIFO access, and host port control and
status registers can be accessed in both host and device modes. When the OTG_FS
controller is operating in one mode, either device or host, the application must not access
registers from the other mode. If an illegal access occurs, a mode mismatch interrupt is
generated and reflected in the Core interrupt register (MMIS bit in the OTG_GINTSTS
register). When the core switches from one mode to the other, the registers in the new mode
of operation must be reprogrammed as they would be after a power-on reset.
33.14.1 CSR memory map
The host and device mode registers occupy different addresses. All registers are
implemented in the AHB clock domain.
Global CSR map
These registers are available in both host and device modes.
Table 205. Core global control and status registers (CSRs)
Acronym
OTG_GOTGCTL
OTG_GOTGINT
OTG_GAHBCFG
OTG_GUSBCFG
OTG_GRSTCTL
OTG_GINTSTS
OTG_GINTMSK
1120/1284
Address
offset
0x000 OTG control and status register (OTG_GOTGCTL) on page 1124
0x004 OTG interrupt register (OTG_GOTGINT) on page 1127
0x008 OTG AHB configuration register (OTG_GAHBCFG) on page 1128
0x00C OTG USB configuration register (OTG_GUSBCFG) on page 1129
0x010 OTG reset register (OTG_GRSTCTL) on page 1131
0x014 OTG core interrupt register (OTG_GINTSTS) on page 1133
0x018 OTG interrupt mask register (OTG_GINTMSK) on page 1137
DocID029473 Rev 3
Register name
RM0430