Figure 101. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6 - ST STM32F413 Reference Manual

RM0430
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The repetition counter is reloaded with the content of TIMx_RCR register
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
•
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.

Figure 101. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6

1.
Here, center-aligned mode 1 is used (for more details refer to
Figure 102. Counter timing diagram, internal clock divided by 2
DocID029473 Rev 3
Advanced-control timers (TIM1&TIM8)
Section 17.4: TIM1&TIM8 registers).
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