Flag Changes; Nmi Interrupt - Renesas M16C Series User Manual

16-bit single-chip microcomputer
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1.2.12.3 Flag changes

When an interrupt request is received, the stack pointer select flag (U flag) changes to "0" and the flag
register (FLG) and program counter (PC) are saved to the stack area indicated by the interrupt stack
pointer (ISP). Thereafter, the interrupt enable flag (I flag) and debug flag (D flag) change to "0" and the
processor interrupt priority level (IPL) at the flag register (FLG) is replaced by the priority level of the
received interrupt. However, when interrupt requests are received for software interrupts 32 to 63, the
flag register (FLG) and program counter (PC) are saved to the stack shown by the stack pointer select
flag (U flag) at the time the interrupt was received. The stack pointer select flag (U flag) does not
change. The value of the processor interrupt priority level (IPL) in the flag register (FLG) differs in the
case of reset, NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and
undefined instruction interrupts. Table 1.12 shows how the IPL changes when interrupt requests are
received.
Table 1.12:
Change of IPL state when interrupt request are accepted
Interrupt
Reset
NMI
DBC
Watchdog timer
Single step
Address match
Software interrupt

1.2.13 NMI Interrupt

An NMI interrupt is generated when the input to the P8
interrupt is a non-maskable external interrupt. The pin level can be checked in the Port P8
5 at address 03F0
16
This pin cannot be used as a normal port input.
Notes:
1. When not intending to use the NMI function, be sure to connect the NMI pin to VCC. Because the NMI
interrupt is non-maskable, it cannot be disabled.
2. When the NMI pin input is "L", do not set the microcomputer in stop mode or wait mode. The NMI
interrupt is triggered by the falling edge, so the "L" level does not need to be maintained longer than
necessary.
Rev.1.00 Sep 24, 2003 Page 34 of 360
Level 0 (000
), is set
2
Level 7 (111
), is set
2
Does not change
Level 7 (111
), is set
2
Does not change
Does not change
Does not change
).
Change of IPL
/NMI pin changes from "H" to "L". The NMI
5
NMI Interrupt
register (bit
5

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