System Management Feature Specifications; System Management Bus; System Management Bus Interface; System Management Interface Signals - Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual

System Management Feature Specifications

6
System Management Feature
Specifications
The Dual-Core Intel Itanium processor 9000 and 9100 series includes a system
management bus (SMBus) interface. This chapter describes the features of the SMBus
and SMBus components.
6.1

System Management Bus

6.1.1

System Management Bus Interface

The processor includes an Itanium processor family SMBus interface which allows
access to several processor features. The system management components on the
processor include two memory components (EEPROMs) and a thermal sensing device
(digital thermometer). The processor information EEPROM (PIROM) is programmed by
Intel with manufacturing and feature information specific to the Dual-Core Intel
Itanium processor 9000 and 9100 series. This information is permanently write-
protected.
EEPROM that is available for other data at the system vendor's discretion. The thermal
sensor can be used in conjunction with the information in the PIROM and/or the Scratch
EEPROM for system thermal monitoring and management. The thermal sensing device
on the processor provides an accurate means of acquiring an indicator of the junction
temperature of the processor core die. The thermal sensing device is connected to the
anode and cathode of the processor on-die thermal diode. SMBus implementation on
the processor uses the clock and data signals as defined by SMBus specifications.
6.1.2

System Management Interface Signals

Table 6-1
signals are used by the system to access the system management components via the
SMBus.
Table 6-1.

System Management Interface Signal Descriptions

Signal Name
3.3V
SMA[2:0]
SMSC
SMSD
SMWP
THRMALERT#
Figure 6-1
how the various system management components are connected to the SMBus. The
reference to the System Board at the lower left corner of
address configuration for multiple processors can be realized with resistor stuffing
options.
® ®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Section 6.2 provides details on the PIROM. The other EEPROM is a scratch
lists the system management interface signals and their descriptions. These
Pin Count
1
3
1
1
1
1
shows the logical schematics of SMBus circuitry on the processor and shows
Description
Voltage supply for EEPROMs and thermal sensor.
Address select passed through from socket.
System management bus clock.
System management serial address/data bus.
Scratch EEPROM write protect.
Temperature alert from the thermal sensor.
Figure 6-1 shows how SMBus
79