Instruction Cache Control; Instruction Cache State At Reset; Enabling/Disabling; Invalidating The Instruction Cache - Intel PXA255 User Manual

4.3

Instruction Cache Control

4.3.1

Instruction Cache State at RESET

After reset, the instruction cache is always disabled, unlocked, and invalidated (flushed).
4.3.2

Enabling/Disabling

The instruction cache is enabled by setting bit 12 in coprocessor 15, register 1 (Control Register).
This process is illustrated in
Example 4-2. Enabling the Instruction Cache
; Enable the Instruction Cache
MRC P15, 0, R0, C1, C0, 0
ORR R0, R0, #0x1000
MCR P15, 0, R0, C1, C0, 0
CPWAIT
4.3.3

Invalidating the Instruction Cache

The entire instruction cache along with the fetch buffers are invalidated by writing to
coprocessor 15, register 7. (See
command.) This command does not unlock any lines that were locked in the instruction cache or
invalidate those locked lines. To invalidate the entire cache including locked lines, the unlock
instruction cache command needs to be executed before the invalidate command. This unlock
command can also be found in
There is an inherent delay from the execution of the instruction cache invalidate command to
where the next instruction will see the result of the invalidate. The following routine can be used to
guarantee proper synchronization.
Example 4-3. Invalidating the Instruction Cache
MCR P15,0,R1,C7,C5,0
CPWAIT
; The instruction cache is guaranteed to be invalidated at this point; the next
; instruction sees the result of the invalidate command.
The Intel® XScale™ core also supports invalidating an individual line from the instruction cache.
See Table 7-12, "Cache Functions" on page 7-9
Intel® XScale™ Microarchitecture User's Manual
Example 4-2, Enabling the Instruction
; Read the control register
; set bit 12 -- the I bit
; Write the control register
; wait for effect, see
Table 7-12, "Cache Functions" on page 7-9
Table 7-14, "Cache Lockdown Functions" on page
; Invalidate the instruction cache and branch
; target buffer
; wait for effect, see
for the exact command.
Instruction Cache
Cache.
Section 2.3.3
for the exact
7-11.
Section 2.3.3
4-5