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Intel PXA273 manual available for free PDF download: Optimization Manual
Intel PXA273 Optimization Manual (144 pages)
PXA27x Processor Family
Brand:
Intel
| Category:
Computer Hardware
| Size: 2.93 MB
Table of Contents
Table of Contents
3
Revision History
9
1 Introduction
11
About this Document
11
Related Documentation
11
High-Level Overview
12
Intel Xscale® Microarchitecture and Intel Xscale® Core
13
Pxa27X Processor Block Diagram
13
Intel Xscale® Microarchitecture Features
14
Intel® Wireless MMX™ Technology
14
Memory Architecture
15
Caches
15
External Memory Controller
15
Internal Memories
15
Processor Internal Communications
15
System Bus
15
Peripheral Bus
16
Peripherals in the Processor
16
Wireless Intel Speedstep® Technology
17
Intel Xscale® Microarchitecture Compatibility
18
Pxa27X Processor Performance Features
18
2 Microarchitecture Overview
21
Introduction
21
Intel Xscale® Microarchitecture Pipeline
21
General Pipeline Characteristics
21
Pipeline Organization
21
Intel Xscale® Microarchitecture RISC Superpipeline
21
Out of Order Completion
22
Use of Bypassing
22
Instruction Flow through the Pipeline
22
Pipelines and Pipe Stages
22
ARM* V5TE Instruction Execution
23
Pipeline Stalls
23
Main Execution Pipeline
23
F1 / F2 (Instruction Fetch) Pipestages
23
Execute (X1) Pipestages
24
Instruction Decode (ID) Pipestage
24
Register File / Shifter (RF) Pipestage
24
D1 and D2 Pipestage
25
Execute 2 (X2) Pipestage
25
Memory Pipeline
25
Multiply/Multiply Accumulate (MAC) Pipeline
25
Write-Back (WB)
25
Behavioral Description
26
Perils of Superpipelining
26
Intel® Wireless MMX™ Technology Pipeline
27
Execute Pipeline Thread
27
ID Stage
27
RF Stage
27
Intel® Wireless MMX™ Technology Pipeline Threads and Relation with Intel Xscale® Microarchitecture Pipeline
27
X1 Stage
28
X2 Stage
28
XWB Stage
28
Multiply Pipeline Thread
28
M1 Stage
28
M2 Stage
28
M3 Stage
28
MWB Stage
28
D1 Stage
29
D2 Stage
29
DWB Stage
29
Memory Pipeline Thread
29
3 System Level Optimization
31
Optimizing Frequency Selection
31
Memory System Optimization
31
Optimal Setting for Memory Latency and Bandwidth
31
External SDRAM Access Latency and Throughput for Different Frequencies (Silicon Measurement Pending)
31
Alternate Memory Clock Setting
32
Internal SRAM Access Latency and Throughput for Different Frequencies (Silicon Measurement Pending)
32
Page Table Configuration
33
Page Attributes for Data Access
33
Page Attributes for Instructions
33
Data Cache and Buffer Behavior When X = 1
33
Optimizing for Instruction and Data Caches
34
Increasing Instruction Cache Performance
34
Data Cache and Buffer Operation Comparison for Intel® SA-1110 and Intel Xscale
34
Round Robin Replacement Cache Policy
35
Code Placement to Reduce Cache Misses
35
Locking Code into the Instruction Cache
35
Increasing Data Cache Performance
35
Cache Configuration
36
Creating Scratch RAM in the Internal SRAM
36
Creating Scratch RAM in Data Cache
37
Reducing Memory Page Thrashing
37
Optimizing TLB (Translation Lookaside Buffer) Usage
38
Reducing Cache Conflicts, Pollution and Pressure
38
Using Mini-Data Cache
38
Optimizing for Internal Memory Usage
39
Buffer for Capture Interface
39
LCD Frame Buffer
39
Buffer for Context Switch
40
Increasing Preloads for Memory Performance
40
OS Acceleration
40
Scratch Ram
40
Optimization of System Components
40
Bandwidth and Latency Requirements for LCD
41
LCD Controller Optimization
41
Frame Buffer Placement for LCD Optimization
43
Arbitration Scheme Tuning for LCD
44
LCD Color Conversion HW
44
LCD Display Frame Buffer Setting
44
Arbiter Functionality
45
Determining the Optimal Weights for Clients
45
Optimizing Arbiter Settings
45
Dynamic Adaptation of Weights
46
Taking Advantage of Bus Parking
46
Peripheral Bus Split Transactions
47
Usage of DMA
47
Memory to Memory Performance Using DMA for Different Memories and Frequencies
47
4 Intel Xscale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
49
Introduction
49
General Optimization Techniques
49
Conditional Instructions and Loop Control
49
Program Flow and Branch Instructions
50
Optimizing Complex Expressions
53
Bit Field Manipulation
54
Optimizing the Use of Immediate Values
54
Optimizing Integer Multiply and Divide
55
Effective Use of Addressing Modes
56
Instruction Scheduling for Intel Xscale® Microarchitecture and Intel® Wireless MMX™ Technology
56
Instruction Scheduling for Intel Xscale® Microarchitecture
56
Scheduling Loads
56
Increasing Load Throughput
59
Increasing Store Throughput
60
Scheduling Load Double and Store Double (LDRD/STRD)
61
Scheduling Load and Store Multiple (LDM/STM)
62
Scheduling Data-Processing
63
Scheduling Multiply Instructions
63
Scheduling SWP and SWPB Instructions
64
Scheduling MRS and MSR Instructions
65
Scheduling the MRA and MAR Instructions (MRRC/MCRR)
65
Scheduling Coprocessor 15 Instructions
66
Instruction Scheduling for Intel® Wireless MMX™ Technology
66
Increasing Load Throughput on Intel® Wireless MMX™ Technology
66
Scheduling the WMAC Instructions
67
Scheduling the TMIA Instruction
68
Scheduling the WMUL and WMADD Instructions
69
SIMD Optimization Techniques
69
Software Pipelining
69
General Remarks on Software Pipelining
71
Multi-Sample Technique
71
General Remarks on Multi-Sample Technique
73
Data Alignment Techniques
73
Porting Existing Intel® MMX™ Technology Code to Intel® Wireless MMX™ Technology
74
Intel® Wireless MMX™ Technology Instruction Mapping
75
Pxa27X Processor Mapping to Intel® Wireless MMX™ Technology and SSE
75
Unsigned Unpack Example
76
Signed Unpack Example
77
Interleaved Pack with Saturation Example
77
Optimizing Libraries for System Performance
77
Case Study 1: Memory-To-Memory Copy
77
Case Study 2: Optimizing Memory Fill
78
Case Study 3: Dot Product
79
Case Study 4: Graphics Object Rotation
80
Case Study 5: 8X8 Block 1/2X Motion Compensation
81
Intel® Performance Primitives
82
Instruction Latencies for Intel Xscale® Microarchitecture
83
Performance Terms
83
Branch Instruction Timings
85
Data Processing Instruction Timings
86
Multiply Instruction Timings
87
Saturated Arithmetic Instructions
88
Load/Store Instructions
89
Status Register Access Instructions
89
CP15 and CP14 Coprocessor Instructions
90
Miscellaneous Instruction Timing
90
Semaphore Instructions
90
Thumb* Instructions
91
Instruction Latencies for Intel® Wireless MMX™ Technology
91
Performance Hazards
93
Data Hazards
93
Resource Hazard
93
Execution Pipeline
94
Multiply Pipeline
95
Memory Control Pipeline
96
Coprocessor Interface Pipeline
97
Multiple Pipelines
97
5 High Level Language Optimization
99
C and C++ Level Optimization
99
Efficient Usage of Preloading
99
Preload Considerations
99
Preload Loop Limitations
101
Coding Technique with Preload
102
Array Merging
104
Cache Blocking
106
Loop Interchange
106
Loop Fusion
107
Loop Unrolling
107
Loop Conditionals
109
If-Else Versus Switch Statements
110
Nested If-Else and Switch Statements
110
Locality in Source Code
110
Choosing Data Types
110
Data Alignment for Maximizing Cache Usage
110
Placing Literal Pools
112
Global Versus Local Variables
112
Number of Parameters in Functions
112
Other General Optimizations
112
6 Power Optimization
115
Introduction
115
Optimizations for Core Power
115
Code Optimization for Power Consumption
115
Switching Modes for Saving Power
115
Normal Mode
115
Deep Idle Mode
116
Deep-Sleep Mode
116
Idle Mode
116
Sleep Mode
116
Standby Mode
116
Wireless Intel Speedstep® Technology Power Manager
117
System Bus Frequency Selection
117
Fast-Bus Mode
118
Half-Turbo Mode
118
Optimizations for Memory and Peripheral Power
119
Improved Caching and Internal Memory Usage
119
SDRAM Auto Power down (APD)
119
External Memory Bus Buffer Strength Registers
119
Peripheral Clock Gating
119
LCD Subsystem
119
Voltage and Regulators
120
Operating Mode Recommendations for Power Savings
120
Idle Mode
120
Normal Mode
120
Deep-Idle Mode
121
Deep-Sleep Mode
121
Sleep Mode
121
Standby Mode
121
Performance Checklist
123
Performance Optimization Tips
123
Power Optimization Guidelines
124
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