Single Channel Dc Biasing Signals; Single Channel Receive Enable Signal (Rcven#); Single Channel Receive Enable Signal Routing Guidelines - Intel Xeon Design Manual

®
Intel Xeon™ Processor and Intel
3.3.7

Single Channel DC Biasing Signals

The DC Biasing signals are DDR signals which are not channel configuration specific. The
following sections describe the DC Biasing signals.
3.3.7.1

Single Channel Receive Enable Signal (RCVEN#)

The Intel E7501 chipset MCH requires a pull-up resistor (Rtt) to DDR VTERM on RCVEN.
Table 20
Table 20. Single Channel Receive Enable Routing Guidelines
Signal Group
Topology
Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing
Trace Length - MCH RCVENIN to Rtt
Termination Resistor (Rtt)
Total Length
Figure 22. Single Channel Receive Enable Signal Routing Guidelines
40
®
E7500/E7501 Chipset Compatible Platform
lists the guidelines. Figure 22
Parameter
MCH
RCVEN_A
summarizes these options.
®
Intel E7501 Chipset MCH
Receive Enable
Pull-up
50 Ω ± 10%
5 mils
15 mils
No Requirement
49.9 Ω ± 1%
No Requirement
DDR VTERM
(1.25V)
49.9 Ω ± 1%
Platform Design Guide Addendum