Dual Channel Receive Enable Signal (Rcven#); Dual Channel Ddrcomp; Dual Channel Receive Enable Signal Routing Guidelines; Receive Enable Routing Guidelines - Intel Pentium M Processor Design Manual

6.3.6.1

Dual Channel Receive Enable Signal (RCVEN#)

®
The Intel
lists the guidelines.
Table 38.

Receive Enable Routing Guidelines

Signal Group
Topology
Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing
Trace Length - MCH RCVENIN to Rtt
Termination Resistor (Rtt)
Total Length
Figure 46.

Dual Channel Receive Enable Signal Routing Guidelines

NOTE: 'x' indicates channel A or B.
6.3.6.2

Dual Channel DDRCOMP

The MCH uses DDRCOMP_x to calibrate the DDR channel buffers. This is periodically done by
sampling the DDRCOMP pin on the MCH. The Intel
24.9 Ω ± 1% pull-down to ground. This may be implemented by routing a 15 mils wide trace to a
resistive network as depicted in
any other terminations.
Table 39.

DDRCOMP Routing Guidelines

Topology
Nominal Trace Width
Nominal Trace Spacing
Trace Length - MCH to Rtt
Termination Resistor (Rtt)
Termination Voltage
Design Guide
®
Intel Pentium
E7501 MCH requires a pull-up resistor (Rtt) to DDR VTERM on RCVEN.
Figure 46 summarizes these options.
Parameter
MCH
RCVEN_x
Figure
Parameter
pull-down
15 mils
20 mils
< 1.0"
24.9 Ω ± 1%
Ground
®
M Processor and Intel
Memory Interface Routing Guidelines
®
Intel E7501 MCH
Receive Enable
Pull-up
50 Ω ± 10%
5 mils
15 mils
No Requirement
49.9 Ω ± 1%
No Requirement
DDR VTERM
(1.25V)
49.9 Ω ± 1%
®
E7501 MCH calibrates using a
47. Place a decoupling capacitor between the pull-down and
®
Intel E7501 MCH
®
E7501 Chipset Platform
Table 38
87