System Design Checklist; Introduction; Host Interface Agtl Bus And Agtl Signals; Agtl Signals - Intel Pentium III Processor 512K Design Manual

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LV Intel Pentium III Processor 512K Dual Processor Platform
7.0

System Design Checklist

7.1

Introduction

This checklist highlights design considerations that should be reviewed prior to manufacturing a
motherboard that implements a LV Intel Pentium
complete list and does not guarantee that a design will function properly.
The following tables contain design considerations for the various portions of a design. Each table
describes one portion and is titled accordingly.
7.2

Host Interface AGTL Bus and AGTL Signals

It is strongly recommended that AGTL signals be routed on signal layers next to the ground layer.
It is important to provide effective signal return paths with low inductance.
Table 20. AGTL Signals (Sheet 1 of 2)
CPU Pin
A[35:3]#
ADS# (AA3)
AERR# (W2)
AP[1:0]#
BERR# (C14)
BINIT# (AF23)
BNR# (L2)
BP[3:2]#
BPM[1:0]
BPRI# (R2)
BR0# (A7)
BR1# (C4)
D[63:0]#
DBSY# (W3)
DEFER# (T3)
DEP[7:0]#
DRDY# (Y1)
HIT# (AA2)
HITM# (U2)
40
III
Connect to chipset and second CPU.
Connect to chipset and second CPU.
Connect to chipset and second CPU. Pull up to VTT through a 150 Ω resistor at
the chipset. See "Wired-OR Signal Considerations" on page 15 for details.
Connect to chipset and second CPU.
Connect to chipset and second CPU. Pull up to VTT through a 150 Ω resistor at
the chipset. See "Wired-OR Signal Considerations" on page 15 for details.
Connect to chipset and second CPU. Pull up to VTT through a 150 Ω resistor at
the chipset. See "Wired-OR Signal Considerations" on page 15 for details.
Connect to chipset and second CPU. Pull up to VTT through a 150 Ω resistor at
the chipset. See "Wired-OR Signal Considerations" on page 15 for details.
Leave as N/C.
Leave as N/C.
Connect to chipset and second CPU.
Connect BR0# from CPU0 to BR1# of CPU1. Connect BR0# of CPU0 to BR0# of
chipset.
Connect BR1# from CPU0 to BR0# of CPU1.
Connect to chipset and second CPU.
Connect to chipset and second CPU.
Connect to chipset and second CPU.
Connect to chipset and second CPU.
Connect to chipset and second CPU.
Connect to chipset and second CPU. Pull up to VTT through a 150 Ω resistor at
the chipset. See "Wired-OR Signal Considerations" on page 15 for details.
Connect to chipset and second CPU. Pull up to VTT through a 150 Ω resistor at
the chipset. See "Wired-OR Signal Considerations" on page 15 for details.
processor 512K system design. This is not a
Pin Connection
Design Guide